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INTEGRATED CIRCUITS
DATA SHEET
PCA8514 Stand-alone OSD
Product specification File under Integrated Circuits, IC14 1995 Nov 27
Philips Semiconductors
Product specification
Stand-alone OSD
CONTENTS 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 8.3 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description SERIAL I/O I2C-bus serial interface High-speed serial interface (HIO) CHARACTER FONTS Character font address map Character font ROM DISPLAY RAM ORGANIZATION Description of display RAM codes Loading character data into display RAM Writing character data to display RAM COMMANDS Command 0 Command 1 Command 2 Command 3 Command 4 Command 5 Command 6 Command 7 Command 8 Command 9 Command A Commands B, C and D Command E Command F Command G 12.1 12.2 12.3 13 13.1 14 15 16 17 18 19 19.1 19.2 19.3 20 21 22 10 10.1 10.2 11 12 MISCELLANEOUS
PCA8514
Space and Carriage Return Codes in different Background/Shadowing modes Combination of character font cells OSD CLOCK OSD CLOCK SELECTION FOR DIFFERENT TV STANDARDS OSD frequency Maximum number of characters per row Maximum number of rows per frame OUTPUT PORTS Mask options DEFAULT VALUES AFTER POWER-ON-RESET LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINES SOLDERING Introduction DIP SO DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1995 Nov 27
2
Philips Semiconductors
Product specification
Stand-alone OSD
1 FEATURES
PCA8514
* Spacing between lines: 4 choices comprising 0, 4, 8 and 12 horizontal scan lines * Display character RAM address auto-post-increment when writing data * Fast I2C-bus serial interface (400 kbaud) or High-speed 3-wire serial interface (1 Mbaud) for data/command transfer * ACM (Active Character Monitor) specifically for use in camcorder applications on word basis; can also be used as a 5th colour control with R, G, B and I signals * Programmable active input polarity of HSYNC and VSYNC * Programmable output polarity of R, G, B, I and FB * Supply voltage: 5 V 10% * Operating temperature: -20 to +70 C * Package: SDIP24 or SO24. 2 GENERAL DESCRIPTION
* Display RAM: 256 x 12 bits * Display character fonts: 128 (fixed in ROM, mask programmable) * Starting position of the first character displayed: 64 vertical and 64 horizontal starting positions can be selected by software * Character size: 4 different character sizes on a line-by-line basis (1 dot = 1H/1V; 2H/2V; 3H/3V and 4H/4V) * Character matrix: 12 x 18 with no spacing between characters and no rounding function * Foreground colours: 16 combinations of Red, Green, Blue and Intensity on character-by-character basis * Background/shadowing modes: 4 modes available, No background, Box shadowing, North-West shadowing and Frame shadowing (raster blanking) on frame basis * Background colours: 16 combinations of Red, Green, Blue and Intensity on word-by-word basis. Available when background mode is in either the Box shadowing, North-West shadowing or Frame shadowing mode * OSD oscillator: on-chip Phase-Locked Loop (PLL) * Character blinking ratio: 1 : 1, 1 : 3 and 3 : 1 (programmable frequency of 116, 132, 164 or 1128 of fVSYNC) on character basis * Display format: flexible display format by using the Carriage Return Code, maximum number of characters per line is also flexible and depends upon the OSD clock frequency 3 ORDERING INFORMATION
The PCA8514 is a member of the PCA85XX CMOS family and is an on-screen character display generator controlled by a microcontroller via the on-chip fast I2C-bus interface or the on-chip High-speed 3-wire serial interface. It is suitable for use in high-end TV or camcorder applications and has also been designed for use in conventional mid-end TV with advanced graphic features.
PACKAGE TYPE NUMBER NAME PCA8514P PCA8514T SDIP24 SO24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT234-1 SOT137-1
1995 Nov 27
3
1995 Nov 27
V DD VSS RESET SCL/SCLK SDA/SIN E HIO/ I2 C I C SLAVE RECEIVER OR HIGH-SPEED I/O RECEIVER
2
4
Philips Semiconductors
handbook, full pagewidth
Stand-alone OSD
BLOCK DIAGRAM
EXTERNAL/INTERNAL DATA SWITCHING BUFFER
CHARACTER SIZE REGISTER/ CONTROL
WRITE ADDRESS COUNTER
ADDRESS BUFFER SELECTOR
DISPLAY CHARACTER RAM
CONTROL REGISTER
HORIZONTAL POSITION REGISTER/ COUNTER VERTICAL POSITION REGISTER/ COUNTER
I/O PORT BUFFERS DISPLAY ROM
3
P00 P01 P04/ACM (VOB2)
4
INSTRUCTION DECODER PLL OSCILLATOR INTERNAL SYNCHRONOUS CIRCUIT C VSYNC HSYNC VSYNC HSYNC CSYNC SEPARATION XTAL2(OUT)
AV DD CONTROL SIGNALS AV SS
CRYSTAL OSCILLATOR
TESTING CIRCUITRY
DISPLAY CONTROL AND OUTPUT STAGE
ACM(VOB2)
12 XTAL1(IN) TEST1 TEST2 TI00 to TI11 R(VOW0) G(VOW1) FB(VOB) I(VOW3)
MLC347
B(VOW2)
Product specification
PCA8514
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Stand-alone OSD
5 5.1 PINNING INFORMATION Pinning
PCA8514
handbook, halfpage
I (VOW3) P04/ACM (VOB2) TEST2 TEST1 C VSYNC HSYNC SDA/SIN SCK/SCLK XTAL1 (IN) XTAL2 (OUT) VSS
1 2 3 4 5 6
24 23 22 21 20 19
AVDD AVSS FB (VOB) V DD B (VOW2) P01 G (VOW1) P00 R (VOW0) HIO/I 2 C E RESET
PCA8514
7 8 9 10 11 12
MGC949
18 17 16 15 14 13
Fig.2 Pin configuration for SDIP24 and SO24.
1995 Nov 27
5
Philips Semiconductors
Product specification
Stand-alone OSD
5.2 Pin description
PCA8514
Table 1 SDIP24 and SO24 packages SYMBOL I (VOW3) P04/ACM (VOB2) TEST2 TEST1 C VSYNC HSYNC SDA/SIN SCL/SCLK XTAL1 (IN) XTAL2 (OUT) VSS RESET E HIO/I2C PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I/O O O I I I/O I I I/O I/O I O I I I I DESCRIPTION Character output signal for intensity control. Port 04 output or Active Character Monitor output (VOB2). Test mode selection; for normal operation TEST2 is connected to VSS. Test mode selection; for normal operation TEST1 is connected to VSS. Capacitor connection for on-chip OSD PLL oscillator. Vertical synchronization input, active polarity programmable. Horizontal synchronization input, active polarity programmable. Data line of the I2C-bus interface or the data line for the High-speed serial interface. Clock line of the I2C-bus interface or the clock line for the High-speed serial interface. System clock input. System clock output. Ground, digital. Master reset input (active LOW). Chip enable (active HIGH) for the High-speed serial interface. When the I2C-bus interface is selected this pin should be connected to VSS. Serial interface selection. When this pin is LOW the High-speed serial interface is selected; when this pin is HIGH the I2C-bus interface is selected. Character output signal: VOW0 for Red. General purpose I/O Port 00. Character output signal: VOW1 for Green. General purpose I/O Port 01. Character output signal: VOW2 for Blue. Power supply, digital. Fast Blanking output (VOB). Ground, analog. Power supply, analog.
R (VOW0) P00 G (VOW1) P01 B (VOW2) VDD FB (VOB) AVSS AVDD
16 17 18 19 20 21 22 23 24
O I/O O I/O O I O I I
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
6 SERIAL I/O
PCA8514
The synchronization process is carried out by on-chip hardware and takes place during the HSYNC retrace period when VSYNC is inactive. The I2C-bus clock is pulled LOW if a complete display RAM data byte is received before HSYNC becomes active. The I2C-bus clock will be released when HSYNC becomes active and then the contents of the shift register will be written into the display RAM location. 6.2 High-speed serial interface (HIO)
The PCA8514 has two means by which it can communicate with a microcontroller: a fast I2C-bus serial interface and a High-speed serial interface. Selection of either interface is achieved via pin 15, HIO/I2C. When HIO/I2C is LOW, the HIO serial interface is selected. When HIO/I2C is HIGH, the I2C-bus serial interface is selected. The PCA8514 is programmed by a series of commands sent via one of these interfaces. There are 16 commands; each command selecting different functions of the PCA8514. The 16 commands are described in detail in Chapter 9. 6.1 I2C-bus serial interface
The High-speed serial interface is selected when pin 15 (HIO/I2C) is pulled LOW. The High-speed serial interface has a 3-wire communication protocol; the maximum transmission rate being 1 MHz. The interface protocol is illustrated in Fig.4 and described below. 1. Pin 14 (E) the chip enable pin is driven HIGH. This LOW-to-HIGH transition clears the shift register and resets the serial input circuit. 2. On the first HIGH-to-LOW transition of SCLK after the interface has been enabled, the first data bit (D0) must be present at the SIN pin. 3. On the following LOW-to-HIGH transition of SCLK, the first data bit (D0) will be latched into the shift register. 4. On the next HIGH-to-LOW transition of SCLK the second data bit (D1) must be present at the SIN pin. Data bit (D1) will be latched into the shift register on the following LOW-to-HIGH transition of SCLK. 5. The operation specified in step 4 above is repeated another 6 times, thus loading the shift register with a complete data byte. This data byte is then transferred to the command interpreter which takes the appropriate action. 6. Providing the chip enable signal remains HIGH, a 2nd data byte can be transferred. The 1st data bit of the next data transfer takes place on the falling edge of the SCLK signal. The following points should be noted: * If the chip enable signal is pulled LOW at any time the shift operation in progress is stopped and the HIO slave receiver is disabled * The rising edge of the chip enable signal resets the HIO slave receiver.
The I2C-bus serial interface is selected by driving pin 15 (HIO/I2C) HIGH. Data transmission conforms to the fast I2C-bus protocol; the maximum transmission rate being 400 kHz. The PCA8514 operates in the slave receiver mode and therefore in normal operation is `write only' from the master device. The format of the data streams sent via the I2C-bus interface is shown in Fig.3. The first data byte is the slave address 1011 101Xb. The last bit of the slave address is always a logic 0, except in the Test mode when it could be a logic 1. Subsequent data bytes contain the commands for control of the device. Upon the successful reception of a complete data byte by the shift register, an Acknowledge bit is sent. A STOP condition terminates the data transfer operation. The I2C-bus interface is reset to its initial state (waiting for a slave address call) by the following conditions: * After a master reset * After a bus error has been detected on the I2C-bus interface. Under both these conditions the data held in the shift register is abandoned. 6.1.1 MAXIMUM SPEED OF THE I2C-BUS
The maximum I2C-bus transmission rate that the PCA8514 can receive is 400 kHz. However, if the data byte being transmitted is for display RAM then internal synchronization of the write operation from the shift register to the display RAM location is necessary. This will reduce the maximum transmission speed.
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
I 2C-bus handbook, full pagewidth bit stream MSB 0 S Slave address LSB 7 8 0 7 W Ack 0 1 1 1 1 0 0 BS O 2nd data byte bit 7 bit 0 8 Ack 0 7 8 Ack nth data byte
MRA818
0
7
8 Ack P
1st data byte Command Register data
Fig.3 I2C-bus write timing diagram - data stream.
handbook, full pagewidth
SCLK
D OUT
E
SCLK
SIN
,, ,, ,, ,,
falling edge of SCLK
D OUT changes
D0
D1
D2
D3
D4
D5
D6
D7
(from HIO master and connected to SIN pin of HIO slave)
Ts rising edge of SCLK
SIN sampled
Th
D0
D1
D2
D3
D4
D5
D6
D7
,, ,, ,, ,, ,,
D0
D1
D2
D3
D4
D5
D6
D7
Ts
D0
D1
D2
D3
D4
D5
D6
D7
,, ,, ,, ,,
MLB395 - 1
(1) Ts 1 s; Th 1 s.
Fig.4 High-speed I/O format.
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
7 CHARACTER FONTS
PCA8514
The file format to submit to Philips for customized character sets is also shown in Fig.7. The following points should be noted: 1. Row 0 of each font is reserved for vertical combination of two fonts. 2. When two font cells are combined in a vertical direction Row 0 of the lower font must contain the same bit pattern as held in Row 18 of the character above it. 3. Binary 1 denotes visual dots; binary 0 denotes a blank space. 4. ROM1 and ROM2 data files are in INTEL hex format on a byte basis. Each byte is structured High nibble followed by Low nibble. 5. The remaining unused 16 bytes (one character font) in ROM1/ROM2 must be filled with FFH. 6. CS denotes Checksum. A software package (OSDGEM) that assists in the design of character fonts on-screen and that also automatically generates the bit pattern HEX files, is available on request. The package is run under the MS-DOS environment for IBM compatible PCs.
128 character fonts may be held in ROM; 125 customer selected fonts and three reserved character font codes. Customer selected fonts are mask programmable. Each character font is stored in a 12 x 19 dot matrix, as shown in Fig.5. Elements in Rows 1 to 18 can be selected as visible dots on the screen; Row 0 is used only for the combination of two characters in a vertical direction, when the North-West shadowing mode is selected (see Sections 9.9 and 10.2). Extremely high resolution can be achieved by having no spacing between characters on the same line and by programming the inter-line spacing to zero. The 12 x 18 dot matrix is suitable for the display of semigraphic patterns, Kanji, Hiragana, Katagana or even Chinese characters. 7.1 Character font address map
Figure 6 shows the character font address map in ROM and RAM. Addresses 7FH and 7EH hold the reserved codes for space and carriage return functions respectively; address 7DH is reserved for testing purposes and addresses (00H to 7CH) contain the character font codes. 7.2 Character font ROM
ROM is divided into two parts: ROM1 and ROM2. The organization of the bit patterns stored in ROM1 and ROM2 is shown in Fig.7.
0
11 10 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
8
7
6
5
4
3
2
1
0
Mask Programmable Font
reserved code
124 (7CH) 125 (7DH) 126 (7EH) 127 (7FH)
MLC350
Test code Carriage return code Space code
MGC948
Fig.5 Character dot matrix organization.
Fig.6 ROM address map.
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
MSB
Column
LSB
11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 3 2 2 3 2 2 3 2 2 3 0 0 5 5 0 0 0 0 00 FC 20 20 FC 20 20 FC 20 20 FF 01 01 53 52 06 0C 58 30 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1
ROM1
000
ROM2
3FC
220 220 3FC 220 220 3FC 220 220 3FF 001 001 553 552 006 00C 058 030
Row
ROM1
:10000000 :10001000 :10002000
byte # 0 1 __ __ __ 5 6__ 7 __8 __9 __ __ __ __ __ __ A B C DE F __ __ 2 3 4 __ 00 00 22 FC 03 22 20 F2 3F 01 20 55 0C 00 03 F F C S <--<--DATA FOR FONT 2 DATA FOR FONT 3 ---> ---> FF CS FF CS
ROM2
: 1 0 0 0 0 0 0 0 FC 03 22 20 C2 3F 20 12 00 53 65 00 58 :10001000 <--:10002000 <--DATA FOR FONT 2 DATA FOR FONT 3 ---> ---> F0 FX FX FF FF C S FF FF C S FF FF C S
MLB345
Fig.7 Character font pattern stored in ROM1 and ROM2.
1995 Nov 27
10
Philips Semiconductors
Product specification
Stand-alone OSD
8 DISPLAY RAM ORGANIZATION 8.1.3 CARRIAGE RETURN CODE
PCA8514
The display RAM is organized as 256 x 12 bits. The general format of each RAM location is as follows. Bits <11-5> hold character data and allow a choice from 125 customer designed character fonts to be selected or one of three reserved codes. Bits <4-0> contain the attributes of the character font, for example colour, character size etc. 8.1 Description of display RAM codes
There are four data formats for display RAM code: 1. Character Font Code 2. Test Code 3. Carriage Return Code 4. Space Code. The above data formats allow great flexibility in the creation of On Screen Displays; see Fig.8. 8.1.1 CHARACTER FONT CODE
If bits <11-5> hold 7EH, then this is the Carriage Return Code. A transparent pattern will be displayed on the screen and the next character will be displayed at the beginning of the next line. Bits <4-3> select the size of the characters to be displayed on the next line. Bits <2-1> determine the spacing between lines of displayed characters. Bit <0> is the End of Display bit and indicates the end of display of the current screen before exhaustion of display RAM (i.e. before the 256th RAM location). The format of the Carriage Return Code is shown in Table 3. 8.1.4 SPACE CODE
If bits <11-5> are in the range (00H to 7CH), then this is a Character Font Code. 1 of 125 customer designed character fonts can be selected. Bits <4-1> determine the colour of the character, a choice of 16 colours being available. Bit <0> determines whether the character blinks or not. The format of the Character Font Code is shown in Table 2. 8.1.2 TEST CODE
If bits <11-5> hold 7FH, then this is the Space Code. A transparent pattern, equal to one character width, will be displayed on the screen. A mask programmable option is available that allows the space character to be transparent or to have a programmable background colour; see Section 13.1. Bits <4-1> determine the background colour of the characters that follow the Space Code in both the Box shadowing and North-West shadowing modes. Bit <0> is the Active Character Monitor (ACM) enable/disable bit. The ACM signal is specifically for use in camrecorder applications where part of the display is to be recorded on tape and displayed on the screen, whilst the remaining part is for display only. Figure 9 shows a typical ACM application. During the back-tracing period R, G, B, I, FB and ACM are inactive. The format of the Space Code is shown in Table 4.
If bits <11-5> hold 7DH, then this is a special code reserved for testing purposes only. Table 2 Format of Character Font Code 11 C6 10 C5 9 C4 8 C3 7 C2 6 C1 5 C0 4 T4 3 T3 2 T2 1 T1 0 T0 Blink
Character Font Code (00H - 7CH) Table 3 Format of Carriage Return Code 11 C6 10 C5 9 C4 8 C3 7 C2 6 C1 5 C0 4 T4
Foreground colour
3 T3
2 T2
1 T1
0 T1 End
Carriage Return Code (7EH) Table 4 Format of Space Code 11 C6 10 C5 9 C4 8 C3 7 C2 6 C1 5 C0
Character size
Line Spacing
4 T4
3 T3
2 T2
1 T1
0 T0 ACM
Space Code (7FH) 1995 Nov 27 11
Background colour
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
Vstart
HI !
SP
TH
I
S
SP
I
S
CR
line spacing 1 = 4H CR line spacing 2 = 8H
T H E SP N E W CR F U N C T I O N CR I N SP P C A 8 5 1 0
Hstart
line spacing 3 = 0H line spacing 4 = 0H
CR
line spacing 4 = 4H
ST
SP
A
NDAL
CR line spacing 6 = 0H CR
WEL
COME
Volume
Channel
MRA832
Four different background colours (in box shadowing mode): BLACK RED GREEN BLUE
Fig.8 Example of On Screen Display.
1995 Nov 27
12
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
Battery Status : OK Shutter speed : 500 Focal Length : 28 mm
Date : July 15, 1994
PHILIPS
Made by MOS IC TAIWAN, PHILIPS
MRA831
In this example, all the characters are displayed on the viewfinder. As only the data 'Date : July 15, 1994' is to be recorded onto the tape, only these characters' ACM attribute bit is set to a logic 1.
Fig.9 Example of ACM signal for use in camrecorder applications.
1995 Nov 27
13
Philips Semiconductors
Product specification
Stand-alone OSD
8.2 Loading character data into display RAM 8.3
PCA8514
Writing character data to display RAM
Three registers are used to address and load data into the display RAM. These registers are described below. 8.2.1 Table 5 7 A7 DCR ADDRESS REGISTER (DCRAR) DCR Address Register 6 A6 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
The procedure for writing character data to the display RAM is as follows: 1. Select the start address in display RAM. The start address can take any value between 0 and 255. Command 3 is used to load the High nibble of the start address. Command 4 is used to load the Low nibble of the start address. The start address is stored in DCRAR. 2. Load the character attributes into DCRTR using Command 2. The actual attribute selected is dependent upon whether the Character Font Code, Carriage Return Code or Space Code has been selected by Command 5 (see Section 8.1). If the attributes of a series of displayed characters are the same, the contents of this register need not be updated. 3. Load the Character Font data into DCTCR using Command 5. This command signals that a complete command byte is available and the data held in registers DCRTR and DCRCR is loaded into the RAM location pointed to by the address stored in DCRAR. The address held in DCRAR is then incremented by `1' pointing to the next RAM location in anticipation of the next operation. A description of all the Commands is given in Chapter 9.
This register holds the address of the location in display RAM into which data is to be written. Command 3 loads the High nibble of the address into this register; Command 4 loads the Low nibble of the address. 8.2.2 Table 6 7 - DCR ATTRIBUTE REGISTER (DCRTR) DCR Attribute Register 6 - 5 - 4 T4 3 T3 2 T2 1 T1 0 T0
The Attribute Register is loaded with character font attribute data using Command 2. The data will be loaded into bits <4-0> of the location in RAM addressed by the contents of DCRAR. Bits 7 to 5 are not used and are reserved. 8.2.3 Table 7 7 - DCR CHARACTER REGISTER (DCRCR) DCR Character Register 6 C6 5 C5 4 C4 3 C3 2 C2 1 C1 0 C0
This register holds the character font data loaded by Command 5. The data will be loaded into bits <12-5> of the location in RAM addressed by the contents of DCRAR.
1995 Nov 27
14
Philips Semiconductors
Product specification
Stand-alone OSD
9 COMMANDS
PCA8514
The PCA8514 is programmed by a series of commands sent by a microcontroller via the I2C-bus interface or the High-speed serial interface. 16 commands (Commands 0 to G) are available for selecting the various functions of the PCA8514. A command overview is shown in Table 8; full descriptions of each command are given in Sections 9.1 to 9.15. Table 8 Command overview (note 1) COMMAND 0 1 2 3 4 5 6 7 8 9 A B C D E F G Command Bank selection Not used in the PCA8514 Character attributes Display Character Address High Display Character Address Low Character font selection - Bank 2 OSD PLL oscillator divisor Scan mode, polarity of FB, ACM, R, G, B and I; OSD enable/disable Polarity of HSYNC and VSYNC, Display mode Blinking frequency, blinking frequency active ratio I/O port selection Vertical start position High Vertical start position Low/ Horizontal start position High Horizontal start position Low Write to ports P00, P01 and P04 Background colour in Frame shadowing mode Enable/disable OSD horizontal stabilization circuit (Regen H), selection of Half-tone background mode and character size of first line BS1 X 0 X 0 0 1 0 0 0 0 0 0 0 0 0 0 0 BS0 X 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 7 0 1 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 6 1 - 0 0 0 C6 0 1 1 1 1 0 0 0 1 1 1 5 1 - 0 1 1 C5 D5 0 0 1 1 0 1 1 X 0 0 4 1 - T4 0 1 C4 D4 0 1 0 1 1 0 1 P04 0 1 3 1 - T3 A7 A3 C3 D3 M1 Hp BF1 0 V5 V1 H3 X R HM3 2 0 - T2 A6 A2 C2 D2 M0 Vp BF0 A/P V4 V0 H2 X G HT2 1 BS1 - T1 A5 A1 C1 D1 Bp S1 BR1 0 V3 H5 H1 P01 B FS1 0 BS0 - T0 A4 A0 C0 D0 EN S0 BR0 0 V2 H4 H0 P00 I FS0
Note 1. `X' denotes don't care state.
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
9.1 Command 0 Command 0 format 6 1 5 1 4 1 3 1 2 0 1 BS1 0 BS0
PCA8514
Table 11 Selection of Foreground colour T4 R 0 0 0 0 0 0 0 0 1 1 1 1 1 4 T4 3 T3 2 T2 1 T1 0 T0 1 1 1 T3 G 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 T2 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 T1 I 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Table 9 7 0
Command 0 is used to select the Command Bank. Bits BS1 and BS0 are the two flags that indicate the current Command Bank being executed. During a master reset these two bits are cleared (BS1 = 0, BS0 = 0). Each command has its own associated Command Bank, this is shown in Table 8. 9.2 Command 1
Command 1 is not used in the PCA8514. 9.3 Command 2
Table 10 Command 2 format BS1 X BS0 0 7 0 6 0 5 0
This command writes character attribute data into the DCR Attribute Register. The actual character attribute is dependent upon the code selected by Command 5. Sections 9.3.1 to 9.3.2 define the character attribute data loaded by Command 2 when Command 5 selects either a Character Font Code, a Carriage Return Code or a Space code. See Tables 2, 3 and 4 for the three code formats. 9.3.1 CHARACTER FONT CODE ATTRIBUTES
Table 12 Selection of Blinking function T0 0 1 BLINKING OFF ON
Command 2 when used in conjunction with a Character Font Code (00H to 7CH) will select 1 of 16 foreground colours and enables/disables the Blinking function.
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
9.3.2 CARRIAGE RETURN CODE ATTRIBUTES
PCA8514
Table 16 Selection of Background colour T4 R 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T3 G 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 T2 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 T1 I 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Command 2 when used in conjunction with the Carriage Return Code (7EH) determines the size of characters to be displayed on the next line, sets the spacing between lines of characters and enables/disables the display. The character size is also a function of the TV scanning standard being used and fOSD; this is explained in Chapter 12. Table 13 Selection of character size T4 0 0 1 1 T3 0 1 0 1 CHARACTER DOT SIZE 1H/1V (the default size) 2H/2V 3H/3V 4H/4V
Table 14 Selection of line spacing T2 0 0 1 1 T1 0 1 0 1 LINE SPACING (BETWEEN TWO ROWS) 0H line 4H line 8H line 12H line
Table 17 ACM control T0 0 1 ACM PIN The ACM pin is inactive; this is also the default setting. The ACM function is active for all characters displayed following this Space Code.
Table 15 End of display control T0 0 1 9.3.3 DISPLAY CONTROL Continue to display next character. This is also the default setting. End of display. SPACE CODE ATTRIBUTES
Command 2 when used in conjunction with the Space Code (7FH) selects the background colour of characters in Box shadowing or North-West shadowing modes and also controls the Active Character Monitor pin. The ACM pin will remain active until a Space Code is received that resets the ACM bit to logic 0. The ACM timing diagram is shown in Fig.10.
1995 Nov 27
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0
18 R G B I FB ACM
SP code
SP code
MRA830 - 1
'S' : Red 'I' : Green 'Z' : Green + Blue + Intensity 'E' : Blue + Intensity 1st SP code : ACM = on 2nd SP code: ACM = off
Fig.10 R, G, B, I - ACM timing.
1995 Nov 27
18
Philips Semiconductors
Product specification
Stand-alone OSD
9.4 Command 3 9.8 Command 7
PCA8514
Table 18 Command 3 format BS1 BS0 0 0 7 0 6 0 5 1 4 1 3 A7 2 A6 1 A5 0 A4
Table 22 Command 7 format BS1 BS0 0 1 7 0 6 1 5 0 4 0 3 M1 2 M0 1 Bp 0 EN
Command 3 loads the DCR Address Register with the 4 MSBs of the RAM address to which data will be written. 9.5 Command 4
This command loads Control Register 1 with data that selects the scanning mode, the output polarity of signals FB, ACM, R, G, B and I, and also enables/disables the OSD clock. With reference to the scanning modes: 1V/2V is the conventional NTSC or PAL scanning mode; 1V/2H is the Line Progress Scan used for the IDTV in NTSC and 2V/2H is for the PAL system and is known as 50 to 100 Hz scan conversion. Table 23 Selection of Scanning Mode M1 M0 0 SCAN MODE 1V/1H; NTSC 525LPF/60 Hz or PAL 625LPF/50 Hz; see Fig.11. This is the default setting. reserved 1V/2H; NTSC 1050LPF/60 Hz; see Fig.11. 2V/2H; PAL 1250LPF/100 Hz; see Fig.12.
Table 19 Command 4 format BS1 BS0 0 0 7 0 6 0 5 1 4 1 3 A3 2 A2 1 A1 0 A0
Command 4 loads the DCR Address Register with the 4 LSBs of the RAM address to which data will be written. 9.6 Command 5
0
Table 20 Command 5 format BS1 BS0 1 0 7 1 6 C6 5 C5 4 C4 3 C3 2 C2 1 C1 0 C0 0 1 1 Command 5 is used to load character data into the DCR Character Register. The data will specify either a Character Font Code, the Test Code, the Carriage Return Code or the Space Code. These codes are explained in detail in Section 8.1. 9.7 Command 6 1 0 1
Table 24 Selection of output polarity (see Fig.13) Bp 0 1 OUTPUT POLARITY (FB, ACM, R, G, B, I) active LOW active HIGH (the default setting)
Table 21 Command 6 format BS1 BS0 0 1 7 0 6 0 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 25 OSD clock control EN 0 1 enabled OSD CLOCK disabled (the default setting)
Command 6 loads the programmable 6-bit counter of the OSD clock oscillator. The output frequency (fOSD) is a function of the decimal value of the 6-bits loaded in by Command 6; see Chapter 11.
1995 Nov 27
19
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
f VSYNC = 60 Hz
f VSYNC = 60 Hz
VSYNC f HSYNC = 15734 Hz HSYNC 262.5 lines (a) Conventional NTSC 1V/1H f VSYNC = 60 Hz VSYNC f HSYNC = 31468 Hz HSYNC 525 lines (b) NTSC 1V/2H 525 lines
MRA834
262.5 lines
f VSYNC = 60 Hz
Fig.11 NTSC scan formats.
handbook, full pagewidth
f VSYNC = 50 Hz
f VSYNC = 50 Hz
VSYNC f HSYNC = 15625 Hz
HSYNC 312.5 lines (a) Conventional PAL 1V/1H 312.5 lines
f VSYNC = 100 Hz VSYNC f HSYNC = 31250 Hz HSYNC 312.5 lines
f VSYNC = 100 Hz
f VSYNC = 100 Hz
f VSYNC = 100 Hz
312.5 lines (b) PAL 2V/2H
312.5 lines
312.5 lines
MRA835
Fig.12 PAL scan formats.
1995 Nov 27
20
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
FB (ACM or R, G, B or I ) Bp = 0 (active LOW) active period active period
FB (ACM or R, G, B or I ) Bp = 1 (active HIGH)
MRA836
Fig.13 Active levels of FB, R, G, B, and I signals.
handbook, full pagewidth
HSYNC/VSYNC Hp/Vp = 0 (active LOW) active period active period
HSYNC/VSYNC Hp/Vp = 1 (active HIGH)
MRA837
Fig.14 Active levels of HSYNC and VSYNC signals.
1995 Nov 27
21
Philips Semiconductors
Product specification
Stand-alone OSD
9.9 Command 8 9.10 Command 9
PCA8514
Table 26 Command 8 format BS1 BS0 0 1 7 0 6 1 5 0 4 1 3 Hp 2 Vp 1 S1 0 S0
Table 29 Command 9 format BS1 BS0 0 1 7 0 6 1 5 1 4 0 3 BF1 2 BF0 1 BR1 0 BR0
Command 8 loads Control Register 2 with data that selects the input polarity of HSYNC and VSYNC (see Fig.14) and also selects the Display modes. Table 27 Selection of input polarity of HSYNC/VSYNC Hp/Vp 0 1 active HIGH INPUT POLARITY active LOW (the default setting)
This command loads Control Register 3 with data that controls both the character blinking frequency and the active ratio of the character blinking frequency. Figures 25 to 29 show how blinking influences the display in different display modes. Table 30 Selection of Blinking frequency BF1 BF0 0 0 BLINKING FREQUENCY (Hz) f VSYNC ---------------- ; this is the default setting 16 f VSYNC ---------------32 f VSYNC ---------------64 f VSYNC ---------------128
Table 28 Selection of Display Mode S1 0 S0 0 DISPLAY MODE Mode 0: this is the No background mode. The OSD characters are superimposed on the TV video signals (see Fig.15). Mode 1: this is the North-West shadowing mode; available only with character sizes 2V/2H or 4V/4H. The shadows are generated as if a light source was placed North-West of the character (see Figs 16 to 18). The shadows generated lie within 18 rows in a vertical direction but can be extended by one bit to the next characters first column, in a horizontal direction (see Figs 19 and 20). Mode 2: this is the Box shadowing mode. A background dot matrix of 12 x 18 bits surrounds the character font; see Figs 21 and 22. Mode 3: this is the Frame shadowing (raster blanking) mode. A background colour fills the whole screen when no bit patterns are being displayed (see Fig.23). 1 of 16 background colours can be selected using Command F; the default background colour is Blue. 0 1
1
0
0
1
1
1
Table 31 Selection of active ratio of character blinking BR1 BR0 0 0 1 1 0 1 0 1 1:1 1:3 reserved ACTIVE RATIO 3 : 1 (the default setting)
1
0
1
1
1995 Nov 27
22
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
MOS
SP code SP code
SP code
scan line
FB R G B I
MLB346
'M' : Red + Blue + Intensity 'O' : Blue 'S' : Red + Green + Intensity Bp = 1
Fig.15 Mode 0: No background mode.
1995 Nov 27
23
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
scan line
: background FB R G B I 1f OSD 1st character: GREEN 2nd character: GREEN + BLUE + INTENSITY background: RED + BLUE Bp = 1 (active HIGH) Available only in character sizes 2V/2H or 4V/4H.
MRA839
Fig.16 Mode 1: North-West shadowing mode.
1995 Nov 27
24
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1H
1V
MRA842
Fig.17 Example of North-West shadowing mode - size 2V/2H.
1995 Nov 27
25
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2H
MRA843
2V
Fig.18 Example of North-West shadowing mode - size 4V/4H.
1995 Nov 27
26
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth 0
1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Character designed in character ROM
Character displayed on TV screen
MRA844
Fig.19 Example of North-West shadowing mode.
1995 Nov 27
27
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
0 1 2 3 4 5 6 7 8 9 10 11
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 10 11
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Two characters designed in character ROM separately 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Two characters displayed on TV screen
MRA846
Fig.20 North-West shadowing.
1995 Nov 27
28
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
Column 0
Column 11
Row 0
Row 17
MRA840
background colour
Fig.21 Mode 2: Box shadowing mode.
1995 Nov 27
29
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
size = 1
handbook, full pagewidth
size = 4 0 1 2 size = 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
10
11
size = 3
MRA847
Fig.22 Example of Box shadowing mode.
1995 Nov 27
30
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
MRA841
Background: BLUE
Fig.23 Mode 3: Frame shadowing mode.
1995 Nov 27
31
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
60 Hz VSYNC 0 1 23 7 8 10 11
60 Hz
14 15 0
1
2
3
7
8
10 11
14 15
Blinking frequency: Blinking ratio: 1 : 3 Blinking frequency: Blinking ratio: 1 : 1 Blinking frequency: Blinking ratio: 3 : 1 Blinking frequency: Blinking ratio: 1 : 3 Blinking frequency: Blinking ratio: 1 : 1 Blinking frequency: Blinking ratio: 3 : 1
f VSYNC 16 f VSYNC 16 f VSYNC 16 f VSYNC 32 f VSYNC 32 f VSYNC 32
MRA848
Fig.24 Timing diagram of character blinking frequency and blinking ratio.
, , ,
1995 Nov 27
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code
Character ON
,, , ,, , ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,,
CR code
,, ,, ,,
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code
Character OFF
,, , ,, , ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,,
CR code
MLB397
Fig.25 Blinking in No background mode.
32
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
,, ,, ,,
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code
Character ON
,, , ,, , ,,,, , ,, ,,, ,, ,, ,, ,,,, ,, ,, ,,, ,,
CR code
,,,
, ,, ,, ,,
SP code
,,, ,, ,,, ,, , ,,,,,, ,,, ,,, ,,, ,,,,,, ,,, ,
CR code
Character OFF
,,, ,, ,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,,
,,,
MLB398
Fig.26 Blinking in North-West shadowing mode.
, , ,
1995 Nov 27
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code
Character ON
,, , ,, , ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,,
CR code
,, ,, ,,
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code
Character OFF
,, , ,, , ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,,
CR code
MLB399
Fig.27 Blinking in Box shadowing mode (Space Code with background).
33
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
, , ,
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code
Character ON
,, , ,, , ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,,
CR code
,, ,, ,,
,,, ,, ,,, ,, ,,, ,,, ,,, ,,, ,,, ,,,
SP code SP code
Character OFF
,, , ,, , ,, ,,,, ,, ,,, ,, ,, ,, ,, ,, ,, ,,,
CR code
MLB400
Fig.28 Blinking in Box shadowing mode (Space Code without background).
SP code
CR code
CR code
Character ON
Character OFF
MLB401
Fig.29 Blinking in Frame shadowing mode.
1995 Nov 27
34
Philips Semiconductors
Product specification
Stand-alone OSD
9.11 Command A 9.13 Command E
PCA8514
Table 32 Command A format BS1 BS0 0 1 7 0 6 1 5 1 4 1 3 0 2 A/P 1 0 0 0
When output ports P00, P01 and P04 are enabled, Command E is used to write data to them. Table 37 Command E format BS1 BS0 7 1 6 1 5 X 4 P04 3 X 2 X 1 0
Command A loads Control Register 4 with data that determines the function of pin 2 (P04/ACM(VOB2)). Table 33 Selection of P04 or ACM A/P 0 PIN FUNCTION P04 is selected as an output port. Data is written to this port using Command E. This is also the default setting. ACM function selected; can also be used as the 5th colour signal. Commands B, C and D
0 9.14
1
P01 P00
Command F
Table 38 Command F format BS1 BS0 0 0 7 0 6 1 5 0 4 0 3 R 2 G 1 B 0 I
1
This command loads Control Register 5 with data that determines the background colour in Frame shadowing mode. 9.15 Command G
9.12
Table 34 Command B format BS1 BS0 0 1 7 1 6 0 5 0 4 1 3 V5 2 V4 1 V3 0 V2
Table 39 Command G format BS1 BS0 0 0 7 0 6 1 5 0 4 1 3 HM3 2 HT2 1 FS1 0 FS0
Table 35 Command C format BS1 BS0 0 1 7 1 6 0 5 1 4 0 3 V1 2 V0 1 H5 0 H4 Command G is used to enable/disable the OSD horizontal stabilization circuit, to select the Half-tone mode and to select the character size of the first line. In the Half-tone mode, excellent semi-transparent half-tone effects can be obtained with OSD frequencies in the range 4 to 7 MHz. This mode also enhances the background colour with intensity output. For further details on the half-tone effect refer to "The programming guide for the PCA8514", report number MICT/AN9402. Table 40 Horizontal stabilization circuit control HM3 0 1 STATE OF STABILIZATION CIRCUIT Stabilization circuit disabled (the default state). Horizontal stabilization circuit enabled.
Table 36 Command D format BS1 BS0 0 1 7 1 6 0 5 1 4 1 3 H3 2 H2 1 H1 0 H0
These three commands determine the vertical and horizontal start positions of the display. 64 vertical and 64 horizontal start positions can be selected. After a master reset, starting positions are not guaranteed and therefore must be programmed by the user. The horizontal start position (HP) and the vertical start position (VP) may be calculated as follows: HP = [ 4 x ( H5 H0 ) + 5 ] x f OSD Where (H5 H0) is the decimal value of these 6 bits and (H5 H0) 4. VP = [ 4 x ( V5 V0 ) ] x number of scan lines Where (V5 V0) is the decimal value of these 6 bits and (V5 V0) 0.
Table 41 Selection of Half-tone mode HT2 0 1 HALF-TONE MODE Half-tone mode not selected (the default state). Half-tone mode available when ACM bit = 1.
1995 Nov 27
35
Philips Semiconductors
Product specification
Stand-alone OSD
Table 42 Selection of the character size for the first line FS1 FS0 0 0 1 1 0 1 0 1 2H/2V 3H/3V 4H/4V CHARACTER DOT SIZE 1H/1V (the default size) 10.2
PCA8514
Combination of character font cells
Two (or more) character font cells may be combined in a horizontal or vertical direction to create a new higher resolution pattern. The combination of two cells in a horizontal direction is straight forward and requires no special precautions to be taken. When combining character cells in this manner all 4 Background/Shadowing modes are available. An example of combining two character font cells in a horizontal direction is shown in Fig.35. However, the combination of two character font cells in a vertical direction is more difficult and care must be taken; otherwise, the new pattern may be created with gaps in its shadowing. An example of a character pattern with gaps is shown in Fig.37. Providing the steps listed below are followed no problems with shadowing will occur. * The line spacing between two rows of characters must be programmed to 0H. This procedure is explained in Section 9.3.2. * If the North-West shadowing mode is selected then when combining two character cells in a vertical direction Row 0 must contain the same bit pattern as held in Row 18 of the character directly above it. This is shown in Fig.38. * If North-West shadowing is not required then Row 0 should contain all zeros.
10 MISCELLANEOUS 10.1 Space and Carriage Return Codes in different Background/Shadowing modes
Figures 30 to 34 show the Space Code and Carriage Return Code in the 4 different Background/Shadowing modes: * Mode 0: the No background mode. Both the Space Code and the Carriage Return Code are displayed as transparent (no bit) patterns with the video signal as the background. This is shown in Fig.30. * Mode 1: the North-West shadowing mode. Both codes are displayed in the same manner as for Mode 0. This is shown in Fig.31. * Mode 2: the Box shadowing mode. The Space Code is displayed as an opaque pattern with a selected background colour. This will also be the background colour of the character following the Space Code. The Carriage Return Code however, is displayed as a transparent (no bit) pattern superimposed on the video signal. This is shown in Fig.32. The Space Code can also be displayed as a transparent pattern on the video signal, and this is shown in Fig.33. The choice of whether the Space Code displays an opaque pattern or a transparent pattern is mask programmable. * Mode 3: the Frame shadowing mode. The Space Code and Carriage Return Code are displayed as transparent patterns with background colour. This is shown in Fig.34.
1995 Nov 27
36
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
RED BLUE
MRA853
Fig.30 Space Code and Carriage Return Code in No Background mode - transparent pattern.
1995 Nov 27
37
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
RED BLUE
BLACK (background) GREEN (background)
MRA854
Fig.31 Space Code and Carriage Return Code in North-West shadowing mode - transparent pattern.
1995 Nov 27
38
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
RED BLUE
YELLOW(background) CYAN (background)
MRA855
SP code is an opaque pattern with the background colour of the character it intends to change or keep. CR code is always a transparent pattern with the video signal as its background. SP code can change the background colour of itself and the character/word next to it (in this example: from cyan to yellow).
Fig.32 Space Code and Carriage Return Code in Box shadowing mode.
1995 Nov 27
39
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
RED BLUE
YELLOW (background) CYAN (background)
MED267
SP code is an transparent pattern with no background colour. CR code is always a transparent pattern with the video signal as its background. SP code can change the background colour the character/word next to it (in this example : from cyan to yellow).
Fig.33 Space Code and Carriage Return Code in Box shadowing mode.
1995 Nov 27
40
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 910 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SP code
CR code
RED BLUE
YELLOW (background)
MRA856
SP and CR codes are both transparent patterns coloured the same as the background colour.
Fig.34 Space Code and Carriage Return Code in Frame shadowing mode.
1995 Nov 27
41
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
1
2
3
4
5
6
7
8
9
10
11 0
1
2
3
4
5
6
7
8
9
10
11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MRA849
Fig.35 Combination of two character cells in a horizontal direction to create a new font.
1995 Nov 27
42
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
0
handbook, full pagewidth
1
2
3
4
5
6
7
8
9
10
11 0
1
2
3
4
5
6
7
8
9
10
11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MRA850
Fig.36 Combination of two character cells in a horizontal direction to create a new font North-West shadowing mode.
1995 Nov 27
43
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
0 1 2 3 4 5 6 7 8 9 10 11
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 0 1 2 If Row 0 of the lower 3 character does not contain 4 the bit pattern of Row 18 5 of the upper character 6 in North West shadowing 7 mode, a gap in the 8 shadow might occur. 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11
MRA851
Character pattern stored in the ROM/RAM
Character pattern displayed on the screen
Fig.37 Combination of two characters in a vertical direction - with gap.
1995 Nov 27
44
Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
0 1 2 3 4 5 6 7 8 9 10 11
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11
0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 0 1 2 Row 0 of the lower character 3 should contain the bit 4 pattern of Row 18 5 6 of the upper character in 7 North West shadowing 8 mode to avoid a 'break' 9 in the shadow 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11
MRA852
Character pattern stored in the ROM/RAM
Character pattern displayed on the screen
Fig.38 Combination of two characters in a vertical direction - with no gap.
1995 Nov 27
45
Philips Semiconductors
Product specification
Stand-alone OSD
11 OSD CLOCK The on-chip clock generator comprises Phase-Locked Loop circuitry and is shown in Fig.39. The frequency of the OSD clock is programmable and is determined by the contents of the 6-bit counter, which is loaded using Command 6. The OSD clock frequency is calculated as shown below; frequencies within the range 4 to 14 MHz can be selected. f OSD = f HSYNC x 16 x ( PLLCN ) Where: 16 < (PLLCN) < 40; (PLLCN) is the decimal value held in the 6-bit counter. The Voltage Controlled Oscillator (VCO) is synchronized to the HIGH-to-LOW edge of f1 (see Fig.39) which is always on the trailing edge of fHSYNC. The programmable active level detector will pass the HSYNC signal if it is programmed as active HIGH or invert the HSYNC signal if it is programmed as active LOW. The 4-bit prescaler increments or decrements the output of the VCO in steps of (16 x fHSYNC).
PCA8514
The OSD clock is enabled/disabled using Command 7; see Section 9.8. When the OSD clock is disabled, the oscillator remains active, therefore the transient time from the OSD clock start-up to locking into the external HSYNC signal is reduced. As the on-chip oscillator is always active after power-on, when the OSD clock is enabled no large currents flow (as for RC or LC oscillators); therefore radiated noise is dramatically reduced. Character width is a function of the OSD clock frequency; decreasing fOSD increases the width of the characters. Therefore, for optimum character display quality the choice of the OSD clock frequency is important; this is explained in Chapter 12.
handbook, full pagewidth
f1
C R1
HSYNC
ACTIVE LEVEL DETECTOR
PHASE/ FREQUENCY DETECTOR
CHARGE PUMP AND LOOP FILTER
VOLTAGE CONTROLLED OSCILLATOR
C1
divided by N
PROGRAMMABLE 6-BIT COUNTER
4-BIT PRESCALER f PLL f OSD
MLC349
OSD disable
Fig.39 Block diagram of OSD oscillator.
1995 Nov 27
46
Philips Semiconductors
Product specification
Stand-alone OSD
12 OSD CLOCK SELECTION FOR DIFFERENT TV STANDARDS 12.1 OSD frequency 12.2
PCA8514
Maximum number of characters per row
The number of characters per row is a function of the OSD clock frequency and the TV standard used. With reference to Fig.40 the active video signal period of a horizontal line is 53.5 s. However, in order to reduce jittering at the screen edge, overscan is normally applied by the TV manufacturer and this reduces the visible video signal period to 48.15 s. The examples given below show how the number of characters per row and the character width may be obtained for the NTSC 525LPF/60 Hz TV standard using different OSD clock frequencies. 12.2.1 NTSC 525LPF/60 Hz; fOSD = 6 MHz
The PCA8514 supports four different TV scanning standards. To obtain the best quality character display, each TV standard requires a different OSD frequency. To cater for this requirement the PCA8514 provides a programmable OSD clock that generates frequencies in the range 4 to 14 MHz. The three examples given below illustrate the OSD clock requirements for different TV scanning standards. 12.1.1 NTSC 525LPF/60 Hz and PAL 625LPF/50 Hz
The OSD clock is applied directly to the OSD circuitry and can take any value within the 4 to 14 MHz frequency range. The NTSC 525LPF/60 Hz standard when used with a 19 inch screen and an OSD clock of 8 MHz, produces a character dot width of 13.2 mm. 12.1.2 NTSC 1050LPF/60 Hz
* As fOSD = 6 MHz: tOSD = 0.1666 s. * The number of visible dots on one horizontal line is 290 (48.15 s/0.1666 s). However, as the starting position of the first character dot is approximately 45 dots after HSYNC, the actual visible number of dots per line is 245. * Each character is composed of a 12 x 18 dot matrix; therefore the maximum number of characters on one line is 20 (245/12). * If a 19 inch TV screen is used, the width of a horizontal line is approximately 370 mm and this gives a character width of 18.5 mm. 12.2.2 NTSC 525LPF/60 Hz; fOSD = 10 MHz
With this standard, in order to obtain the same character dot width as in the NTSC 525LPF/60 Hz standard that uses an OSD clock of 7 MHz; the OSD clock must be doubled to 14 MHz because the horizontal frequency is doubled. To keep the same character height as that in the NTSC 525LPF/60 Hz standard, HSYNC is also divided by two, internally. 12.1.3 PAL 1250LPF/100 Hz
* As fOSD = 10 MHz: tOSD = 0.1 s. * The number of visible dots on one horizontal line is 481 (48.15 s/0.1 s). Allowing for the initial starting position of 45 dots, the actual number of visible dots per line is 436. * Each character is composed of a 12 x 18 dot matrix; therefore the maximum number of characters on one line is 36. * With a 19 inch TV screen, the width of a horizontal line is approximately 370 mm and the character width is 10.3 mm.
With this standard, in order to obtain the same character dot width as in the PAL 625LPF/50 Hz standard; the OSD clock must be doubled. HSYNC is applied directly to the OSD circuitry without being divided by two as both the horizontal frequency (1250 Hz) and the vertical frequency (100 Hz) are doubled.
1995 Nov 27
47
Philips Semiconductors
Product specification
Stand-alone OSD
12.3 Maximum number of rows per frame 12.3.2 PAL 625LPF/50 HZ
PCA8514
The number of rows per frame is a function of the number of active lines per display field and the number of vertical dots in the character matrix (which is 18). The number of rows per frame (N) is calculated as shown below. number of active lines per field N = -------------------------------------------------------------------------------18 The four examples shown below illustrate how the maximum number of rows per frame is obtained for each TV scanning standard. 12.3.1 NTSC 525LPF/60 HZ
The number of active lines per field for this standard is 280. Therefore, the maximum number of rows per frame is 15. 12.3.3 NTSC 1050LPF/60 HZ
For this standard the number of active lines per frame is double that of the NTSC 525LPF/60 Hz standard. However, as HSYNC is divided by two internally, the maximum number of rows per frame is also 13. 12.3.4 PAL 1250LPF/100 HZ
The number of active lines per field for this standard is between 241.5 and 249H (see Fig.41). If the value of 241 is used then the maximum number of rows per frame is 13.
With this standard it is not necessary to divide HSYNC by two as both the horizontal and vertical frequency are doubled. The maximum number of rows per frame is 15.
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handbook, full pagewidth
1995 Nov 27
blacker than black, 100% blanking level 75% black, 67.5 2.5% composite video signal white, 12.5 2.5% 0
Philips Semiconductors
Stand-alone OSD
49
RIGHT horizontal deflection sawtooth trace 0 retrace LEFT
retrace begins blanking begins
blanking ends retrace ends
MRA862
Product specification
PCA8514
Fig.40 Composite video signal for three horizontal lines compared to three horizontal deflection sawteeth (NTSC 525LPF/60 Hz).
handbook, full pagewidth
1995 Nov 27
equalizing pulse interval blacker than black black level white level zero carrier picture horizontal blanking bottom of picture 3H 3H 3H (12.5 0% vertical blanking 0.05 V 0.03 V 0 start of next field 2.5)% vertical sync pulse interval equalizing pulse interval H H H 0.5 H H 0.5 H H 100% (75 2.5)% first field, 262.5 H 16.666 s or 1/60 s RIGHT horizontal deflection sawtooth LEFT active lines 241.5 to 249.5 H vertical blanking period 13 to 21 H (825.5 to 1335.5 s) active lines 241.5 to 249.5 H vertical blanking period 13 to 21 H
MRA863
Philips Semiconductors
Stand-alone OSD
second field, 262.5 H 16.666 s or 1/60 s
50
BOTTOM vertical deflection sawtooth trace blanking begins retrace 500 to 750 s
second field vertical deflection sawtooth
trace retrace
TOP
first field vertical deflection sawtooth
blanking ends
Product specification
PCA8514
Fig.41 Vertical synchronization and blanking pulse intervals for one frame (NTSC 525LPF/60 Hz).
Philips Semiconductors
Product specification
Stand-alone OSD
13 OUTPUT PORTS The three output ports P00, P01 and P04 can be configured using one of three mask options. The three output mask options are specified below: Option 1 Standard output with switched pull-up current source. See Figs 42 and 45.
PCA8514
Option 2 Open-drain output. See Figs 43 and 46. Option 3 Push-pull output. See Figs 44 and 47. The state of each output port after a Power-on-reset can also be selected using the mask options. All the available mask options for the PCA8514 are given in Section 13.1.
handbook, full pagewidth
Port output register TR2 current source D MQ D SQ SQ TR1 V SS
VDD TR3 TR4 100 A typical Pin
write pulse data bus
MBE128
read pulse (testing use only)
Fig.42 Standard output with switched pull-up current source (Option 1 - P00 and P01).
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
Port output register
handbook, full pagewidth
write pulse data bus
V DD D MQ D SQ Pin SQ TR1 VSS
MBE129
read pulse (testing use only)
Fig.43 Open-drain output (Option 2 - P00 and P01).
Port output register
handbook, full pagewidth
VDD TR2 current source TR3 TR4 100 A typical Pin TR1 V SS
MBE130
write pulse data bus
D
MQ
D
SQ SQ
read pulse (testing use only)
Fig.44 Push-pull output (Option 3 - P00 and P01).
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
ACM output from OSD circuit VDD
ACM output enable (A/P bit) Port output register write pulse data bus TR2 current source
TR3 TR4 100 A typical Pin
D
MQ
D
SQ SQ TR1 V SS
MLB353 - 1
read pulse (testing use only)
Fig.45 Standard output with switched pull-up current source (Option 1 - P04).
handbook, full pagewidth
ACM output from OSD circuit
ACM output enable (A/P bit) Port output register write pulse data bus VDD
D
MQ
D
SQ Pin TR1 VSS
MLB354 - 1
read pulse (testing use only)
Fig.46 Open-drain output (Option 2 - P04).
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
handbook, full pagewidth
ACM output from OSD circuit VDD
ACM output enable (A/P bit) Port output register write pulse data bus TR2 current source
TR3 TR4 100 A typical Pin
D
MQ
D
SQ
TR1 V SS
MLB355 - 1
read pulse (testing use only)
Fig.47 Push-pull output (Option 3 - P04).
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Philips Semiconductors
Product specification
Stand-alone OSD
13.1 Mask options
PCA8514
Table 46 Customer selected mask options FEATURE Output port configurations P00 P01 P04 Port state after Power-on-reset P00 P01 P04 Oscillator tranconductance LOW MEDIUM HIGH Space Code pattern Transparent Opaque P00 P01 P04 OPTION
Tables 43 to 47 list the available mask options for the PCA8514. Table 46 is intended for customer use when ordering the device. Table 43 Port configuration options OPTION 1, 2 or 3 1, 2 or 3 1, 2 or 3 PORT
Table 44 Port state after Power-on-reset OPTION HIGH HIGH HIGH or LOW Table 45 Space Code options OPTION Transparent pattern Opaque pattern SHADOWING MODE Available in Box shadowing mode only; see Fig.33. Available in Box shadowing mode only; see Fig.32. PORT P00 P01 P04
Table 47 System oscillator transconductance options OPTION LOW (gmL) MEDIUM (gmM) HIGH (gmH) TRANSCONDUCTANCE (mS) 0.7 1.6 4.5 fOSC - QUARTZ CRYSTAL (MHz) 1 to 6 4 to 12 - fOSC - CERAMIC RESONATOR (MHz) - 1 to 6 3 to 16
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Philips Semiconductors
Product specification
Stand-alone OSD
14 DEFAULT VALUES AFTER POWER-ON-RESET
PCA8514
The default values of registers after a Power-on-reset are specified in Table 48. All other settings must be initialized by the user after a Power-on-reset. Table 48 Default values REGISTER BIT STATE AFTER RESET DESCRIPTION
User directly controllable registers Control Register 1 M1 M0 Bp EN Control Register 2 Hp Vp S1 S0 Control Register 3 BF1 BF0 BR1 BR0 Control Register 4 Control Register 5 A/P R G B I - BS1 BS0 User indirectly controllable registers ACM Background colour ACM B R G I Character size End of display T4 T3 T0 0 1 0 0 0 0 0 0 The default character size is 1V/1H. A different value can be selected by using the Carriage Return Code. Will continue to display next character (if the OSD clock is enabled). The ACM output is LOW unless changed by the Space Code. The Background colour selected is Blue unless changed by the Space Code. 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Command Bank selection bits. Command Bank 00 is selected. Scanning mode selection bits. Conventional NTSC 525LPF/60 Hz and/or PAL 625LPF/50 Hz selected. Polarity control bit; the output polarities of FB, ACM, R, G, B and I are active HIGH. OSD enable/disable control bit; the OSD is disabled. HSYNC input polarity control bit; the input polarity is active LOW. VSYNC input polarity control bit; the input polarity is active LOW. Display mode selection bits; the North-West shadowing mode is selected. Blinking frequency control bits. The blinking frequency is set to fVSYNC/16 Hz. Active ratio of blinking frequency control bits. The active ratio is set to 3 : 1. Port control bit. Pin 2 (P04/ACM/VOB2) is selected as an output port pin. Background colour selection bits in Frame shadowing mode; the default colour is Blue.
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Philips Semiconductors
Product specification
Stand-alone OSD
15 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI IOH IOL Ptot Tstg Tamb supply voltage all input voltages maximum source current for all port lines maximum sink current for all port lines total power dissipation storage temperature operating ambient temperature PARAMETER MIN. -0.5 -0.5 - - - -55 -20
PCA8514
MAX. +7.0 VDD + 0. 5 -5.0 5.0 500 +125 +70 V V
UNIT
mA mA mW C C
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
16 DC CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = -20 to +70 C. All voltages with respect to VSS unless otherwise specified. SYMBOL VDD IDD PARAMETER operating supply voltage operating supply current VDD = 5 V; fxtal = 3 MHz; fOSD = 10 MHz VDD = 5 V; fxtal = 3 MHz; fOSD = Stop VDD = 5 V; fxtal = 3 MHz; fOSD = Stop RESET, TEST1, TEST2, HSYNC, VSYNC, E and HIO/ I2C inputs VIL VIH ILI VIL VIH ILI IOL IOH1 IOH2 VIL VIH IOL IOL IOH1 IOH2 LOW level input voltage HIGH level input voltage input leakage current VSS < VI < VDD 0 0.01 - 0.3VDD V VDD V A 0.7VDD - CONDITIONS - - - MIN. 4.5 TYP. 5.0 5 7 1 MAX. 5.5 10 14 2 UNIT V mA mA mA
0.20 10 - -
Ports P00 to P03 (with combined functions) inputs LOW level input voltage HIGH level input voltage input leakage current VSS < VI < VDD VDD = 5 V; VO = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS SDA/SIN and SCK/SCLK inputs LOW level input voltage HIGH level input voltage 0 - 0.3VDD V VDD - - - -400 - V 0.7VDD - VDD = 5 V; VO = 0.4 V VDD = 5 V; VO = 0.4 V VDD = 5 V; VO = 0.7VDD VDD = 5 V; VO = VSS 3.0 - 0 - 0.3VDD V VDD 10 - - -400 - V A 0.7VDD -
Ports P00 to P03 (with combined functions) outputs LOW level output sink current HIGH level pull-up output source current 5.0 -40 - 12.0 -100 -140 -7.0 mA A A mA
HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -3.0
SDA/SIN and SCK/SCLK outputs LOW level open-drain sink current mA
R, G, B, I, FB and P04/ACM outputs LOW level push-pull output sink current HIGH level pull-up output source current 3.2 -40 - 5.5 -100 -140 -2.4 mA A A mA
HIGH level push-pull output source current VDD = 5 V; VO = VDD - 0.4 V -1.6
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Philips Semiconductors
Product specification
Stand-alone OSD
17 AC CHARACTERISTICS VDD = 5 V 10%, VSS= 0 V. SYMBOL fxtal fOSD PARAMETER crystal oscillator frequency OSD oscillator frequency note 1 1V/1H scanning mode 1V/2H and 2V/2H scanning modes COSD ROSD Note external capacitance at pin C external resistance at pin C CONDITIONS MIN. 0.5 4.0 4.0 0.4 5.0 TYP. 3.0 7.0 12.0 - -
PCA8514
MAX. 6.0 10.0 14.0 4.0 15.0
UNIT MHz MHz MHz F k
1. The minimum frequency should be 3 times greater than the maximum I2C-bus frequency or the HIO frequency used in the system.
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Philips Semiconductors
Product specification
Stand-alone OSD
18 PACKAGE OUTLINES SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
PCA8514
SOT234-1
D seating plane
ME
A2
A
L
A1 c Z e b 24 13 b1 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT234-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 22.3 21.4 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
ISSUE DATE 92-11-17 95-02-04
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Philips Semiconductors
Product specification
Stand-alone OSD
PCA8514
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
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Philips Semiconductors
Product specification
Stand-alone OSD
19 SOLDERING 19.1 Introduction
PCA8514
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 19.3.2 WAVE SOLDERING
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 19.2 19.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 19.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 19.3 19.3.1 SO REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Stand-alone OSD
20 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCA8514
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 21 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD46 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
453061/1100/01/pp64 Document order number: Date of release: 1995 Nov 27 9397 750 00469

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